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| PDU18F 8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F) FEATURES * * * * * * * * Digitally programmable in 256 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting Precise and stable delays Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability Fits standard 40-pin DIP socket Auto-insertable N/C OUT/ OUT EN/ GND N/C N/C N/C GND N/C N/C N/C N/C GND N/C EN/ A7 IN N/C GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC N/C A0 A1 A2 VCC N/C A3 A4 A5 VCC N/C N/C N/C N/C VCC N/C A6 N/C N/C data 3 delay devices, inc. PACKAGES PDU18F-xx DIP PDU18F-xxC5 Gull-Wing PDU18F-xxM Military DIP PDU18F-xxMC5 Military Gull-Wing FUNCTIONAL DESCRIPTION The PDU18F-series device is a 8-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A7-A0) according to the following formula: TDA = TD0 + TINC * A PIN DESCRIPTIONS IN OUT OUT/ A0-A7 EN/ VCC GND Delay Line Input Non-inverted Output Inverted Output Address Bits Output Enable +5 Volts Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS * * * * * * * * Programmed delay tolerance: 5% or 2ns, whichever is greater Inherent delay (TD0): 13ns typical (OUT) 12ns typical (OUT/) Setup time and propagation delay: Address to input setup (TAIS): 10ns Disable to output delay (TDISO): 6ns typ. (OUT) Operating temperature: 0 to 70 C Temperature coefficient: 100PPM/C (excludes TD0) Supply voltage VCC: 5VDC 5% Supply current: ICCH = 65ma ICCL = 128ma Minimum pulse width: 6% of total delay DASH NUMBER SPECIFICATIONS Part Number PDU18F-.5 PDU18F-1 PDU18F-2 PDU18F-3 PDU18F-4 PDU18F-5 PDU18F-6 PDU18F-8 PDU18F-10 Incremental Delay Per Step (ns) .5 .3 1 .5 2 .5 3 1.0 4 1.0 5 1.5 6 1.5 8 2.0 10 2.0 Total Delay Change (ns) 127.5 6.4 255 12.8 510 25.5 765 38.3 1,020 51.0 1,275 63.8 1,530 76.5 2,040 102.0 2,550 127.5 NOTE: Any dash number between .5 and 10 not shown is also available. 1997 Data Delay Devices Doc #97006 1/30/06 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 PDU18F APPLICATION NOTES ADDRESS UPDATE The PDU18F is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation: TOAX = max { (Ai - A i-1) * TINC , 0 } where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed. A similar situation occurs when using the EN/ signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to "clear" itself. This is achieved by holding the EN/ signal high and the IN signal low for a time given by: TDISH = Ai * TINC Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TDISH has elapsed. INPUT RESTRICTIONS There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. A7-A0 TAENS EN/ TENIS IN TDA OUT A i-1 TOAX PW IN PW OUT TSKEW TDISO TAIS Ai TDISH OUT/ Figure 1: Timing Diagram Doc #97006 1/30/06 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 PDU18F DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER Total Programmable Delay Inherent Delay Output Skew Disable to Output Low Delay Address to Enable Setup Time Address to Input Setup Time Enable to Input Setup Time Output to Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TDT TD0 TSKEW TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN MIN TYP 255 14.0 1.5 6.0 UNITS TINC ns ns ns ns ns ns 2.0 10.0 8.0 See Text See Text 12 32 200 6 16 100 % of TDT % of TDT % of TDT % of TDT % of TDT % of TDT TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VCC VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short-circuit Output Current Output High Fan-out Output Low Fan-out SYMBOL VOH VOL IOH IOL VIH VIL VIK IIHH IIH IIL IOS MIN 2.5 TYP 3.4 0.35 MAX 0.5 -1.0 20.0 2.0 0.8 -1.2 0.1 20 -0.6 -150 25 12.5 UNITS V V mA mA V V V mA A mA mA Unit Load NOTES VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX -60 Doc #97006 1/30/06 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 PDU18F PACKAGE DIMENSIONS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 .580 MAX. .010 .002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 .650 MAX. 2.100 Lead Material: Nickel-Iron alloy 42 TIN PLATE .320 MAX. .015 TYP. .018 TYP. .100 TYP. .070 MAX. DIP (PDU18F-xx, PDU18F-xxM) .020 TYP. .040 TYP. .010.002 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 .710 .590 .00 MAX. .882 .00 .007 .00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 .090 1.100 2.080.020 .100 .320 MAX. .050 .01 Gull-Wing (PDU18F-xxC5, PDU18F-xxMC5) Doc #97006 1/30/06 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 PDU18F DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 4.5 x Total Delay OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf 10% 1.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) OUT IN TRIG TIME INTERVAL COUNTER Test Setup PERIN PW IN TRISE INPUT SIGNAL 2.4V 1.5V 0.6V TFALL VIH 2.4V 1.5V 0.6V VIL TDAF TDAR OUTPUT SIGNAL 1.5V VOH 1.5V VOL Timing Diagram For Testing Doc #97006 1/30/06 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 |
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